1. Field of the Invention
The present invention relates to a static random access memory (hereinafter abbreviated as SRAM) cell and a manufacturing method thereof, and more particularly, to a SRAM cell with beta ratio larger than 1 and a manufacturing method thereof.
2. Description of the Prior Art
In recent years, with widespread use of mobile terminal equipment, digital signal processing in which bulk data such as sounds or images is processed at high speed has been increasingly important. SRAM, which is capable of high-speed access processing, holds an important place as a semiconductor memory device to be mounted on such mobile terminal equipment.
Each of SRAM cells include a bistable circuit, which does not require refreshing. The switching speed of each bistable circuit is determined by the resistance and capacitance of the control electrodes of the transistors and the connection of the transistors within the circuit, thereby determining the slew rate of its output voltage. In a conventional six-transistor SRAM (hereinafter abbreviated as 6T-SRAM) cell including two pull-up transistors, two pull-down transistors, and two access transistors. One of the pull-up transistors and one of the pull-down transistors are electrically connected in series to constitute an inverter. The ratio of the conductance of the inverters to the conductance of the pass-gates of a SRAM cell is a basic metric used to measure the stability of the cell, i.e., the ability of the SRAM cell to retain its data state. This ratio is referred as the beta (β) ratio of the SRAM cell. The larger the beta ratio is, the more stable the cells are. Since the beta ratio of an SRAM cell can be approximated by the ratio of μeff (W/L) of gate of the pull-down transistor to μeff (W/L) of the pass-gate of the accesses transistor, same width and length dimension of gates of the pull down transistors and pass-gates of the access transistors let beta ratio close to 1. And it is also found that current crowding and low speed in such SRAM cell.